A simplified process for fabricating an integrated circuit comprises the steps of developing a product idea, designing a circuit, fabricating the circuit, packing and assembling the product. The circuit design process can be further refined to include the steps of refining the product idea, creating a logic schematic, and verifying the functionality of a circuit layout. As manufacturing processes have decreased below 50 nanometers, circuit layouts more frequently fail to meet design requirements during functional verification of the circuit layout. These failures may be due to the close proximity of the circuit elements, which increases parasitic components (e.g., parasitic capacitance, parasitic resistance and parasitic inductance). The parasitic components delay the propagation of electrical signals through the circuit and may cause signal integrity problems, preventing the circuit from meeting the design requirements. If the circuit design fails to meet the design requirements, the designer must modify the circuit design and retest the new design until all design requirements are met. This repetitive process adds additional cost to the process and delays the completion of the design.
A wire model may be utilized to determine the parasitic effects of the circuit design, in order to help avoid expensive redesign later in the design process. Silicon foundries or cell library vendors may develop the wire model from statistical information taken from various sample designs. However, in specific designs, a wire model may not be available, and the designer may be required to know the distributed resistance and capacitances of the wires. In addition, the wire models are complex, cumbersome, and time consuming to develop and use.
Considering the foregoing, it would be desirable to provide a system and method for generating a wire model without complex functions that would allow a designer to vary the accuracy of the model depending on given requirements. Furthermore, other desirable features and characteristics will become apparent from the following detailed description and the appended claims taken in conjunction with the accompanying drawings and this Background.